Sensing a phase change memory is always a challenge especially when the reference cell and the target cell of the phase change memory are both located at high resistance range. The traditional way of sensing a phase change memory is to provide a voltage to generate a cell current signal. When the target cell resistance and the reference resistance get higher, the cell current signals flowing through the target cell and the reference cell are too small to verify a voltage difference between the target cell and the reference cell.
The conventional method of developing a cell signal (Vcell) has the following sequence:
Providing a clamping voltage of VClamp with any kind of pre-charge scheme for setting up a bit line voltage (VBL);
Generating a cell current (Icell), wherein Icell relates to a bitline voltage and a cell state, and the cell state is the resistance of phase change memory (RPAR+Rcell), where RPAR is the parasitic resistance and Rcell is the resistance of the cell;Setting Icell=VBL/(RPAR+Rcell); and
Developing a cell voltage VCell for being provided to a sense amplifier, wherein VCell=ICell*RLoad, where RLoad is the resistance of the load. This sequence can be accomplished by a circuit as shown in FIG. 1. FIG. 1 is a schematic circuit diagram of a portion of a conventional sensing circuit on a target cell side for a phase change memory. In FIG. 1, it includes a load having a resistance RLoad with a first and a second terminals, a clamping switch MC with a first, a second and a control terminals, a parasitic resistor with a resistance RPAR and a cell resistor with a resistance Rcell, wherein the first terminal of the load receives a power voltage and the second terminal of the load is electrically connected to the first terminal of the clamping switch MC at a first node for outputting a cell voltage Vcell, the control terminal of the clamping switch receives a clamping voltage Vclamp, and the second terminal of the clamping switch MC is electrically connected to the first terminal of the parasitic resistor at a second node for providing a bitline voltage VBL, wherein the clamping switch is a MOSFET MC with the first terminal being a drain, the second terminal being a source, and the control terminal being a gate, and VBL=VClamp−VgsMC, where VgsMC is the voltage difference between the gate and the source of the MOSFET MC.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicant finally conceived a cell sensing circuit for a phase change memory and methods thereof.